`timescale 1ns/1ns
module FSM_tb;
	reg		[1:0]	in;
	reg				clk;
	reg				rst;
	wire	[3:0]	out;
	
	FSM U1(.clk(clk), .rst(rst), .in(in), .out(out));
	
	initial begin
	clk = 1; rst = 1; in = 00;
	#15 rst = 0;
	#10 rst = 1;
	#10 in = 2'b10;
	#10 in = 2'b00;
	#10 in = 2'b11;
	#10 #10 #10 #10 in = 2'b00;
	#10 in = 2'b11;
	#10 in = 2'b00;
	end
	
	always begin
	#5 clk = ~clk;
	end
	
endmodule